Memristor-Based In-Memory Computing Architecture for Energy-Efficient Deep Neural Network Acceleration
DOI:
https://doi.org/10.63665/IJAICE.0203.14Keywords:
Memristor, In-Memory Computing, Processing-in-Memory, Deep Neural Networks, DNN Accelerator, Resistive RAM, ReRAM, Crossbar Array, Neuromorphic Computing, Energy-Efficient Computing, Vector–Matrix Multiplication, Hardware Acceleration, Artificial Intelligence, Non-Volatile Memory, Hardware–Algorithm Co-DesignAbstract
The rapid expansion of deep neural networks has created a growing demand for computing platforms capable of delivering high inference performance within increasingly restricted energy and memory budgets. Conventional computing systems separate storage and computation, requiring model parameters and intermediate activation data to travel repeatedly between memory and processing units. This movement introduces latency, consumes additional energy, and becomes particularly restrictive when neural networks are deployed in edge and embedded environments. This research presents a memristor-based in-memory computing architecture intended to reduce this overhead by combining non-volatile weight storage with massively parallel computation. The proposed architecture employs memristive crossbar arrays in which neural-network parameters are represented by programmable conductance states. Input activations are applied to the array, while the resulting electrical responses are accumulated to perform vector–matrix multiplication within the memory structure. Peripheral conversion circuits, digital control logic, programmable weight mapping, precision management, and error-compensation mechanisms are incorporated to form a complete accelerator architecture. The research further considers device variability, conductance nonlinearity, limited precision, analog noise, and peripheral conversion overhead because these factors strongly influence the practical benefits of analog in-memory computing. A hardware–algorithm co-design methodology is introduced to determine suitable crossbar dimensions, parameter mapping strategies, numerical precision, and compensation methods for representative deep-learning workloads. The proposed framework is evaluated using inference accuracy, latency, energy per inference, throughput, memory utilization, and energy–delay product as principal performance indicators. The resulting analysis indicates that integrating storage and computation can substantially reduce the frequency of data transfers between conventional memory and processing elements. The architecture is therefore particularly relevant to edge artificial intelligence, embedded machine learning, intelligent sensors, Internet-of-Things systems, and other applications in which computational efficiency and energy consumption are important design constraints.
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