Adaptive Edge-AI Hardware–Algorithm Co-Design for Ultra-Low-Power Real-Time Intelligent Electronic Systems
DOI:
https://doi.org/10.63665/IJAICE.0203.13Keywords:
Edge Artificial Intelligence, Hardware–Algorithm Co-Design, TinyML, Embedded AI, Ultra-Low-Power Computing, Neural Architecture Search, Model Compression, Quantization, Structured Pruning, Hardware Acceleration, Energy-Efficient AI, Embedded Systems, Real-Time Inference, Intelligent Electronics, Edge ComputingAbstract
The rapid expansion of intelligent sensors, connected electronic devices, autonomous systems, and embedded computing platforms has increased the demand for artificial intelligence models that can operate directly on devices with limited computational and energy resources. Conventional cloud-oriented artificial intelligence architectures are not always suitable for these environments because continuous data transmission can introduce communication delays, increase energy consumption, create privacy concerns, and make system operation dependent on network availability. Edge artificial intelligence provides an alternative by moving inference closer to the data source, but effective deployment requires simultaneous consideration of model complexity, memory capacity, processor capability, execution latency, and energy consumption. This paper proposes an adaptive hardware–algorithm co-design framework for ultra-low-power real-time intelligent electronic systems. The framework combines lightweight neural network architectures, hardware-aware neural architecture search, structured model pruning, adaptive quantization, memory-aware execution, and runtime configuration selection. Unlike conventional approaches in which the neural network and embedded hardware are optimized independently, the proposed framework establishes a continuous relationship between algorithmic requirements and hardware characteristics. Candidate models are evaluated according to predictive accuracy, memory requirement, inference latency, energy consumption, and computational demand. A resource-aware selection mechanism subsequently chooses a suitable model configuration according to the available device resources and workload conditions. The proposed design is intended for microcontroller-based systems, embedded processors, low-power accelerators, intelligent sensors, and Internet-of-Things devices. The evaluation framework considers accuracy, latency, peak memory, model storage, energy per inference, throughput, and energy–delay characteristics. The proposed architecture provides a practical pathway toward scalable and energy-conscious Edge-AI deployment in next-generation intelligent electronic systems.
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